A display device (liquid crystal panel, etc.) charges the capacitor of a pixel circuit selected using scanning lines and input signal lines with a signal voltage supplied from a source driver via an input signal line, so that the necessary colors and brightnesses are represented by each pixel.
For example, when a high-potential-side voltage VGH of 30V is supplied to a scanning line in each pixel circuit, the TFT transistor of each pixel circuit is turned on, and a charging operation is performed in which the capacitor of each pixel circuit is charged up to a signal voltage supplied to the input signal line. A further example is when a low-potential-side voltage VGL of −5V is supplied to the scanning line, the TFT transistor is turned off, and a holding operation in which the charged voltage of the capacitor is held is performed. The charging operation and a holding operation are alternately repeated.
In the liquid crystal panel, flicker and color variations occur depending on the position of a panel. The flicker and color variations occur as a result of the slope of the decrease in scanning line potential becoming shallower with increasing distance from a gate driver due to a parasitic capacitance between the scanning line and a panel substrate, and because the slope of the decrease in scanning line potential differs depending on the panel position, a feed-through voltage in a TFT transistor of each pixel circuit in the same scanning line varies.
The feed-through voltage is a difference between the charged voltage of a capacitor during the charging operation of the pixel circuit and the charged voltage of the capacitor during the holding operation. The steeper the slope of the decrease in scanning line potential, the more the voltage of the capacitor during the holding operation is decreased due to the influence of the parasitic capacitance, and the feed-through voltage increases.
Accordingly, a driving unit of a liquid crystal panel, which is provided with a voltage adjustment circuit (gate voltage shaping circuit) that causes the slope of the decrease in scanning line potential to become shallow in order to ensure that the driving unit is not easily affected by parasitic capacitance, has been proposed.
FIG. 1 illustrates an example of the related art of a voltage adjustment circuit that adjusts a power-supply voltage supplied to a gate driver for driving the scanning lines of a liquid crystal panel in order to reduce the decrease in scanning line potential.
This voltage adjustment circuit includes a delay setting circuit 1, a slope adjustment circuit 2, and a clamp voltage adjustment circuit 3, and a control logic 4 of the delay setting circuit 1 performs opening/closing control of switch circuits 5a to 5c based on a control signal CTL.
When the control signal CTL reaches a high level (hereinafter referred to as H level), the switch circuit 5a is turned on. As illustrated in FIG. 3, for example, an output voltage VGHM that has a similar potential as the high-potential-side power supply voltage VGH of 30V is output to the gate driver as a power supply, and the capacitor CL is charged up to the voltage VGH level.
When the control signal CTL reaches a low level (hereinafter referred to as L level), the switch circuit 5a is turned off, and the switch circuit 5b is turned on. The output voltage VGHM starts to fall after a delay time period t1 set by the capacitor CE of the delay setting circuit 1 starting from the decrease in the level of the control signal CTL. Then, the output voltage VGHM decreases at a rate adjusted by the capacitor CL and the resistor RE of the slope adjustment circuit 2.
When the output voltage VGHM decreases to a clamp voltage VCLP set by the clamp voltage adjustment circuit 3, the clamp voltage VCLP is maintained and increases up to the voltage VGH again at the next rise of the control signal CTL, and the above-described operations are repeated.
The above-described output voltage VGHM of the voltage adjustment circuit is supplied as a power supply to the gate driver, and the gate driver controls the scanning lines based on a scanning line driving voltage GVS. Due to the voltage adjustment circuit operations, the rate of decrease in the scanning line driving voltage GVS decreases, and variations in the feed-through voltage of each pixel circuit in the same scanning line are suppressed.
Furthermore, a display device has been proposed in which, by controlling the rate of decrease in scanning line driving voltage, it is possible to avoid the flicker that occurs in the vertical direction of a liquid crystal panel (see Japanese Laid-open Patent Publication No. 2008-145677).
The voltage adjustment circuit is configured in such a manner that the capacitor CL is charged/discharged by the slope adjustment circuit 2 in order to generate an output voltage VGHM, and the gate driver is driven using the output voltage VGHM. Thus, a capacitor CL that has a large capacitance is necessary.
Furthermore, the delay setting circuit 1 is configured in such a manner that a capacitor CE formed as an externally provided element is used in order to adjust the delay time period t1 of the decrease in output voltage VGHM. The slope adjustment circuit 2 is configured in such a manner that a resistor RE formed as an externally provided element is used in order to adjust the rate of decrease in output voltage VGHM. Then, the capacitor CE is used to adjust a delay time period t1 for increasing a scanning line driving voltage GVS up to a high-potential-side voltage VLH. The resistor RE is used to adjust the slope of the decrease in output voltage VGHM in order to eliminate flicker and color variations.
Therefore, since the resistor RE of the externally provided element is necessary, problems arise in that the voltage adjustment circuit becomes large, and also, the cost increases. Furthermore, in a case where the slope of the decrease in output voltage VGHM is to be re-adjusted, some problems are that replacement of the resistor RE is necessary and also, only uniform adjustment may be performed for each scanning line.